Semiconductor And Packaging Advancements That Are Critical For Optoelectronics
The world is speeding ahead towards global connectivity with advancements in 5G, IoT, and Wi-Fi, where the total amount of data created, captured, copied, and consumed globally was forecasted to reach 64.2 zettabytes in 2020 ― a number that is expected to double by 2025. All of this data must be seamlessly backhauled to and from the “cloud” the “5G core” or just the infrastructure of data centers meant to support this ever-increasing demand. While much of this is data center-to-user and data center-to-data center traffic (23 percent), the vast majority of this is traffic that remains within the datacenter. Supporting this global demand wirelessly has yielded technological leaps in smart spectrum usage, cell tower density, and even the use of non-terrestrial infrastructure, leveraging satellites as a tool for our networking needs. This densification can also be seen in terms of the fiber infrastructure and within data centers where adopting high speed Ethernet is necessary to expand data center capacity.
Data centers are already phasing out of transceivers 10G and below and shifting from 40G to 100G transceivers. According to YoleDéveloppement, the optical transceiver market is expected to grow from $9.6 billion in 2020 to $20.9 billion in 2026, primarily driven by high data rate modules of 100G and beyond. This is all in spite of the COVID-19 pandemic where the needs for e-commerce, e-conferencing, cloud services, and video streaming only increased.
The optical component problems that crop up with the increasing data density
So how are OEMs, mobile network operators (MNOs), and data centers expected to support this newfound traffic load? The solutions vary for higher data rate 100G and beyond Ethernet where hyperscale data centers are already looking ahead at 400G.
In the pluggable module, switch ASICs connect to a retimer (clock-and-date recovery) that synchronizes the data from the switch to the optical interface. The switching ASIC communicates to the transceiver through a metallic trace on the PCB which is increasingly lossy at high frequencies. As data rates increase, the length and loss of the trace make a retimer between the ASIC and transceiver module necessary. Today’s Ethernet switch application specific integrated circuits (ASICs) have shifted to utilizing 56G PAM-4 SerDes for a 56 Gb/s lane rate with up to 256 ports for 12.8 Tb/s on a singular chip. Up to 25.6 Tb/s can also be achieved with 64 integrated 50G PAM4 or even 32 100G PAM4 SerDes cores. Despite the slowing of Moore’s law, some of these ASICs are achieved using extremely small 7nm CMOS processes. However, these Ethernet switches must have a multiplicity of pluggable module ports on their front panel and twice as many electrical traces within to support the data rate.
Outside of light source
integration with the SiP PICs, future packaging advancements with integration
of the electronic integrated circuit (EIC) and photonic integrated circuit
(PIC) will enable a continued reduction in size while meeting power consumption
Outside of light source
This has led to the potential shift from the standard pluggable module with a separate switching ASIC and pluggable optics to an embedded optics has strong potential to increase data center density. This can be accomplished with either an on-board optics module with the switching ASIC or by having the optical transceiver co-packaged with the switching ASIC. More immediate attempts to meet density, power consumption, bandwidth and data rate requirements, 100G-per-lambda increases the amount of information each data stream can carry with the PAM4 modulation format.
Achieving the longer reach distances for 100G and beyond with single-wavelength optics
In order to meet 100G/400G transport optics at 500 m to 100 km distances within smaller chipsets, companies are left with costly parallel optics in multiple-transceiver solutions or the extremely tight design tolerances in order to utilize the coherent method. Single-lambda technology offers an alternative to these solutions by both lowering the lane/optical component count while extending the transmission range cost-effectively.
Single-mode optical transceivers require coherent light sources that allow for more transmission distance but are only supported by expensive coherent light sources such as Fabry-Perot (FP) and Distributed Feedback (DFB) lasers. Current popular 100 Gb/s optical standards include the 100GBASE-LR4, 100G-PSM4, and 100G-CWDM4 where the latter two cannot offer link distances at 500 m and 2 km, respectively. The 100GBASE-LR4 technologies for a 10 km reach consist of 4 multiplexed wavelengths over a single fiber with LAN-WDM (LWDM) with tightly spaced wavelengths and independent bit streams that are multiplexed before transmission over a multi-mode fiber (MMF) cable and de-multiplexed at the receiver. While this can leverage cheaper light sources such as incoherent LEDs and less precisely aligned vertical cavity surface emitting lasers (VCSELs), LWDM can still only be realized with complex temperature-controlled hermetic packaging for optimal laser functionality and multiple optical components for every lane. The frequency-selective devices for photonic integrated circuits (PICs) with Indium Phosphide (InP) and Silicon photonics (SiP) are highly temperature sensitive due to the thermo-optic coefficients of the semiconductors.
What is single-lambda or single-wavelength optics?
The popular 100 Gbps standards rely on 25 Gb/s optical lanes that align with 25 Gb/s and 50 Gb/s serializer/deserializer (SERDES) standards used in the switching ASIC found on the pluggable module. Each lane comes with its own respective optics. In order to meet 100 Gbps speeds, optical transceivers require four lanes causing the vast majority of the cost of these modules to be associated with optical components. This is in contrast to previous 10G Ethernet pluggable modules where a singular lane of 10 Gbps data could be transmitted/receive with a singular laser and photodiode.
The goal of single-lambda is to shift from the current usage of NRZ (or PAM2) two-level binary modulation format to PAM4 multilevel signal modulation format. This way, each data stream can carry twice the amount of information ― the optical components used to support 50G NRZ would then support 100G PAM4. Similar to the PSM4, LR4, and CWDM4 where NRZ signals are used, a PAM4 signal can be multiplexed on a singular wavelength via an optical engine. This paradigm shift is particularly important in shifting to 400G speeds where generating the optics for 8 lanes at 50 Gbps is costly and complex. The 100G Lambda multi-source agreement agrees that a singular optical lane of 100 G costs at least 40% less than four lanes of 25G with specifications released for 100 Gbps interfaces with reaches up to 40 km (100G-ER1-40) based on a single 100G lane over single-mode fiber (SMF).
A Look Semiconductor and Packaging Advancements Making this Shifts
Photonic integration techniques with compound semiconductors and SiP
The 100G-per-lambda optical transceivers must achieve a high bandwidth and sufficient linearity for PAM4 calling for both design optimizations and smarter packaging techniques. III-V semiconductor substrates with high electron mobility such as Indium Phosphide (InP) and Gallium Arsenide (GaAS) as well as advancing Silicon photonics (SiP) form the building blocks for optical components such as high frequency laser-modulator chips, splitters, and waveguide multiplexers. High speed semiconductor substrates allow for the monolithic integration of light sources with the photonic integrated circuit (PIC) with electric-optic modulators, photodetectors, and passive photonic components. This eliminates the losses at the interface between the light source and the PIC allowing for the chip-scale integration of coherent wavelength division multiplexed (WDM) systems. This however, comes at a cost where SiP systems offer a more scalable alternative with volume Si CMOS production. Integrating these high-performance III-V light sources into SiP while maintaining a low power consumption, small footprint, and high efficiency/simple thermal management is a considerable design challenge.
Integrating the Light Source with SiP PICs
One of the most common solutions for laser integration with SiP include a hybrid integration with III-V lasers with laser flip-chipping requiring both known good laser die and known good SiP die. Other solutions include a “photonic” wirebond technique as well as natively growing direct-bandgap compound semiconductors on the Silicon substrates. The latter technique is still in its infancy due to the potential contamination issues of the fab, thermal constraints due to a limited access to the laser through the SiP chip, and the potential to ruin an entire known good SiP chip with potentially defective lasers. A common topology involves the CMOS-compatible comb laser that generating an optical frequency comb with a fixed carrier spacing through mode locked laser (MLL). The harmonics of these signals are correlated to each other and beat to generate a desired carrier reference signal with a high-speed photodiode (often composed of Germanium on Silicon). Optical losses occur at the light source and laser interface and at the SiP fiber-to-chip coupler requiring the use of amplification with an erbium doped fiber amplifier (EDFA), a semiconductor optical amplifier (SOA), or a transimpedance amplifier (TIA). Integra Optics, for instance, has already released several QSFP28 100G modules that support LWDM wavelengths in the 1310 nm window with an integrated silicon optical amplifier (SOA) and a prismatic dispersion (PD) filter-based design in order to meet the QSFP28 power consumption specifications. These transceivers are able to achieve 80 km distances with forward-error correction (FEC). Meeting the tight power constraints and frequency tolerances required in LWDM with SiP.
SiP Integration of EIC and PIC
Outside of light source integration with the SiP PICs, future packaging advancements with integration of the electronic integrated circuit (EIC) and photonic integrated circuit (PIC) will enable a continued reduction in size while meeting power consumption constraints. A number of 2D, 3D, and 2.5D integration techniques exist for the combing the electronic integrated circuit (EIC) and photonic integrated circuit (PIC) spanning between wire bonding directly to the PCB, flip-chip bumps that can be used to interface between flipped dies and ball grid arrays (BGAs), where the BGAs can interface to a PCB via a photonic interposer (Figure 1). Monolithic integration of the EIC and PIC in SiP is a highly complex process that often suffers from high waveguide loss, with low photodiode responsivity and bandwidth overshadowing the benefit of minimizing parasitics. The 2D configurations with wirebonding however, have to consider serious losses and noise from the parasitic inductance of the wire bonds. Both 2.5D and 3D configurations strike a balance between these two extremes by mitigating packaging parasitics and maximizing the transceivers I/O bandwidth economically.
A combination of smart photonic design, fabrication and packaging practices are required in order to keep up with the global traffic demands. These demands for both wireless and wired connectivity to the cloud are set to soar with an increase in 4K HD video streaming and up-and-coming bandwidth-hungry applications such as VR/AR, tactile internet, haptic communications and autonomous vehicles. Optoelectronics will rely on more semiconductor and packaging advancements for increased integration not only between the photonic components, but also with their respective EICs and even with the switching ASICs in order to minimize the losses and parasitics that come with traces and wirebonds. However, more immediate optical transceiver circuit optimization is required for the adoption of the 100G-per-lambda optics.